1. Field of the Invention
This invention relates to an integrated circuit structure formed with a local interconnect. More particularly, this invention relates to a silicon integrated circuit structure having a tungsten local interconnect.
2. Description of the Related Art
Conventionally an integrated circuit structure may be constructed with local interconnects formed in between adjacent conductive portions of the integrated circuit devices, such as in between the source/drain electrodes of adjacent MOS transistors. Such local interconnects may be formed using the same conductive material as the filler material, e.g., tungsten, used to fill the contact openings which provide electrical connection to other portions of the integrated circuit structure.
With the shrinking of the minimum feature size of integrated circuit structures, the scaling down of the interconnect becomes important to increase the chip density. Tungsten local interconnect is a technology which allows designers of integrated circuit structures to use the first tungsten contact layer as a circuit routing layer, and thus increase the chip density and routing flexibility. However, conventional tungsten local interconnect technology does not allow the tungsten lines at the contact layer level to go across unrelated polysilicon and diffusion regions. That is, conventional tungsten local lines or "interconnects" cannot bridge over conductive regions, but can only be used to interconnect adjacent conductive regions separated by an insulator, and therefore, are conventionally referred to as "local" interconnects. This represents a significant limitation to the use of tungsten interconnect technology as a circuit routing layer.
In copending Pasch et al. U.S. patent application Ser. No. 09/081,403, filed by one of us with another on May 18, 1998, and assigned to the assignee of this invention, and the incorporation of which herein by reference is hereby made, a structure is described and claimed to overcome this problem. A plurality of dielectric layers is provided with the lowest dielectric layer formed over the underlying integrated circuit structure to a height or thickness as high as, or preferably exceeding, the height of the highest conductive regions of the underlying integrated circuit devices; a second dielectric layer is formed above the first dielectric layer with one or more local interconnects formed in this second dielectric layer; and then a thin third dielectric layer is formed over the second dielectric layer and the local interconnects therein. The first layer of metal interconnects is then formed over the thin third dielectric layer.